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Cache memory
Results: 1188

#	Item
591	Trace Analysis for Block-level Caching in Cloud Computing Systems Pim Van Riezen, Lennard Zwart {pi,lennard}@cloudvps.com Cloud VPS Dulcardo Arteaga, Ming Zhao Add to Reading List Source URL: www.cloudvps.nl Language: English - Date: 2013-02-26 05:56:46 Cache Computer memory CPU cache Central processing unit Computer storage Solid-state drive IOPS Smart Response Technology Lookup table Computing Computer hardware Computer performance
592	Understanding application performance via micro-benchmarks on three large supercomputers: Intrepid, Ranger and Jaguar Abhinav Bhatelé, Lukasz Wesolowski, Eric Bohm, Edgar Solomonik and Laxmikant V. Kalé Department of C Add to Reading List Source URL: charm.cs.illinois.edu Language: English - Date: 2011-05-01 22:22:28 Parallel computing Computer memory Jaguar Memory bandwidth Opteron CPU cache Blue Gene Multi-core processor Cray XT5 Computing Computer hardware Supercomputers
593	Avoiding Tree Saturation in the Face of Many Hotspots with Few Buffers Bradley C. Kuszmaul William H. Kuszmaul Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2015-02-18 01:45:03 Cache Central processing unit Computer memory Hash table AMD 10h Logarithm Bloom filter Virtual Output Queues Mathematics Switches Computing CPU cache
594	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:04:57 Central processing unit Chunk CPU cache Parallel computing C dynamic memory allocation Computer memory Computing Computer hardware
595	SigRace: Signature-Based Data Race Detection Abdullah Muzahid University of Illinois at Urbana-Champaign, USA Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-04-25 12:09:23 Central processing unit Parallel computing Concurrency control Threads Computer memory Multithreading OpenMP CPU cache Context switch Computing Concurrent computing Computer architecture
596	Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas University of Illinois at Urbana Champaign http://iacoma.cs.uiuc.ed Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-03-29 16:25:52 CPU cache Dynamic random-access memory Refresh rate Cache Three-phase Computer memory Computer hardware Computing
597	Alpha[removed]and Alpha 21066A Microprocessors Hardware Reference Manual Order Number: EC–QC4GB–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:11 Central processing unit Computer buses Computer memory Conventional PCI Interrupts DEC Alpha Alpha 21064 CPU cache PCI Express Computer hardware Computer architecture Computing
598	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing ∗ Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou University of Illinois at Urbana-Champaign {sarangi,liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Computing CPU cache Data dependency Branch misprediction Branch predictor Instruction set Memory disambiguation Computer hardware Central processing unit Computer engineering
599	Alpha[removed]Microprocessor Hardware Reference Manual Order Number: EC–QP99C–TE Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:02:14 Central processing unit Computer memory CPU cache Cache DEC Alpha PALcode Control register Alpha 21164 Alpha 21364 Computing Computer architecture Computer hardware
600	To appear in the Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA-29) May 2002 ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-06-11 11:28:32 Fault-tolerant computer systems Computer architecture RAID Binary arithmetic Parity Parity bit Application checkpointing CPU cache SGI Origin Computer memory Computer hardware Computing

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